yann98700的部落格

Gtech library:
(為virtual library，可用來看電路合出來會變成什麼東西，而非真有此gate) 
　Gtech is a virtual library. this is what your circuit first gets translated into, before it gets synthesised to technology-defined gates. 
　It does not mean that your real target library will have these gates. 
　It is useful in the sense you can see broadly what kind of circuit, your VHDL ends up with.

Q:When synthesizing RTL to netllists, Synopsys Design Compiler will read GTECH lib to generate a technology-independent netlist if no specific lib assigned. What's the file format for GTECH lib? Where can I see the GTECH file?(哪裡可以看GTECH的檔案)
 
A1:GTECH is just the format of the database synopsys uses, I think that's impossible to see that,

  that must be encrypted when it is saved.
A2:GTECH is in .db format, typically libraries used in Synopsys can be two types 
   1. Synopsys Liberty format : human readable format, you can refer to there documentation 
      for further details.
   2. Synopys database formate ( i.e .db format) : This is an encrypted format of the liberty format.
   As suggest by joe2moon may find it in the synopsys installation directory
A3:You can find it unfer the tool install directory,
   $install_dir > find . -name "gtech.db" 

(若是對已經指明target lib的module設dont touch，it will be fine；但若對RTL module設dont touch，就會產生gtech cell在netlist中)
If the module to which you applied constraint dont_touch is a library specific cell instatiated module..
it will be fine...(means that module is already a netlist for target libary) , otherwise the GTECH netlist wont be mapped into target library...


Designware library: 
(實際的implementation，為function optimized，DC會依照code所寫去挑它覺得最適合的用)  


Designware library is a real implentation for a complicated function like multiplier, divider etc.. 
it is an function-optimized ,but technology independent, macro that gets instantiated if your code implies (or explicity instanitates) an arithmetic 
or some other standard function. 
Means you really dont need to know how to build a booth multiplier or a priority encoder etc; you just write your code so that this functionality is reqiured, 
synopsys will throw in the best-fit hardware implementation it knows (and you have paid for) for that function 
==============================================
2012.7.10新增：
因為又忘記，所以又查了一次。得到資料一份大陸的doc檔，
 http://www.google.com.tw/url?sa=t&rct=j&q=dw_foundation.sldb&source=web&cd=2&ved=0CFoQFjAB&url=http%3A%2F%2Fwww.dianyuan.com%2Fblog%2Fu%2F2009-04%2F298138_1240536972.doc&ei=tZD7T8u5KouVmQW-xMyoBQ&usg=AFQjCNGZCOVF_pgdP6QriBuUTTqJA3FiFA
 
簡介其內容如下：

dw_foundation.sldb
為synopsys提供的Design Ware Library，是technology-independent的"soft macros"。不同製程皆可用。
   (例如adders, mul, comparators等)
可透過target library合成出gates。
幫助user將大的、複雜的、算術的(e.g. pipeline design, div, sin/cos, square root)運算能被合成。
  => 幫助提高電路性能和減少合成時間。

*target_library：為合成的目標庫，由foundry提供，通常放slow.db。
*synthetic_library：有這個library的話就是放design ware library，dw_foundation.sldb。
*link_library：鏈接庫，DC在synthesis後，網表(netlist)時用來參考的library，當有使用synthetic_library時，要將dw_foundation也放入link_lib中。